In order to take advantage of both the fast switching rates of bipolar transistors and the low power consumption of MOS transistors, bipolar and MOS transistors can be combined on the same chip to form what is commonly known as BiCMOS circuitry. In other arrangements, systems are designed that have both bipolar circuits and MOS circuits. In either case, it is often necessary to address the difference in the logic level swings associated with the two transistor types so as to resolve the problems which this difference can cause. Translators circuits are known to effect that transition. A conventional emitter coupled logic (ECL)-to-CMOS translator comprises a complementary ECL input stage including an emitter follower based level shifter and a CMOS output stage. In some ECL to CMOS applications, such as a mobile writer for driving an H-bridge circuit, the translator can be required to translate 300 mV range ECL signals about an order of magnitude higher to a CMOS signal range of about 4 to 5 Volts.
Translators inherently introduce delay; that is, it takes time to switch between bipolar logic levels and CMOS logic levels. As transistors become increasingly small in order to achieve the faster transmission rates needed, the corresponding differential swings associated with their logic outputs are reduced. Accordingly, as known in the art, since conventional translator designs tradeoff speed and gain, conventional translators can become the bottleneck in systems they are used in because the translator is generally slower, and can be significantly slower, as compared to the downstream logic functions that are coupled to receive the gained output provided by the translator.